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STV7617, STV7617D, STV7617U
PLASMA DISPLAY PANEL SCAN DRIVER
FEATURE
s
s s s s s
s s s
64/65 SELECTABLE OUTPUT PLASMA DISPLAY DRIVER 100 V ABSOLUTE MAXIMUM SUPPLY 5 V SUPPLY FOR LOGIC 100/850 mA SOURCE/SINK OUTPUT 700 mA SOURCE/SINK OUTPUT DIODE 65-bit BIDIRECTIONAL SHIFT REGISTER (8 MHz) HIGH IMPEDANCE OUTPUT CONTROL BCD TECHNOLOGY 100-PIN TQFP PACKAGE WITH INTEGRATED HEATSINK
TQFP100 (14 x 14 x 1.4 mm Slug-down) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7617D
TQFP100 (14 x 14 x 1.4 mm) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7617
DESCRIPTION The STV7617 is a scan driver for Plasma Display Panel (PDP) implemented in ST's proprietary BCD technology. Using a 65-bit cascadable 8 MHz shift register, it drives 65 high current & high voltage outputs. The STV7617 can be configured either in 64 or 65 outputs depending on the SEL input Pin. By serially connecting several STV7617, any vertical pixel definition can be performed. The STV7617 is supplied with a separated 90V power output supply and a 5 V logic supply. All command inputs are CMOS compatible. The STV7617 package is a 100-pin TQFP with integrated heatsink located on the bottom (STV7617D) or top (STV7617U) of the package. It is also available without heatsink (STV7617).
TQFP100 (14 x 14 x 1.4 mm Slug-up) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7617U
Version 4.1
June 2000
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
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TABLE OF CONTENTS
PIN CONNECTIONS (SLUG-UP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PIN CONNECTIONS (SLUG-DOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PIN CONNECTIONS (NO SLUG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AC TIMING REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AC TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 INPUT/OUTPUT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PACKAGE MECHANICAL DATA (SLUG-DOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL DATA (SLUG-UP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PACKAGE MECHANICAL DATA (NO SLUG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
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STV7617, STV7617D, STV7617U
PIN CONNECTIONS (SLUG-UP)
(TQFP100 Slug-up)
OUT64 OUT65 SOUT VSSLOG VSSLOG OUT1 77 OUT2 76
75 74 73 72 71 70 69 68 67 66 65
STB
CLK
SEL
BLK
VSSP
VSSP
VSSP
VSSP
SIN
F/R
HIZ
VCC
VPP
VPP
VPP 79
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT33 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100
78
VPP
NC
NC
OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27
STV7617U
TQFP100 (Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 OUT30
49 OUT29
OUT38
OUT37
OUT36
OUT35
OUT34
OUT33
OUT32
OUT31
OUT28
VSSP
VSSP
VSSP
VSSP
VSSSUB
VSSP
VPP
VPP
VPP
VPP
NC
NC
NC
NC
50
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STV7617, STV7617D, STV7617U
PIN CONNECTIONS (SLUG-DOWN)
(TQFP100 Slug-down)
OUT65 77 OUT64 76 SOUT OUT2 OUT1 VSSLOG VSSLOG STB CLK SEL BLK VSSP VSSP VSSP VSSP
SIN
HIZ
F/R
VCC
NC
NC 80
VPP
VPP
VPP 79
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
78
VPP
75 74 73 72 71 70 69 68 67 66 65
OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT33 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39
STV7617D
TQFP100 (Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 OUT36
49 OUT37
OUT28
OUT29
OUT30
OUT31
OUT32
OUT33
OUT34
OUT35
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OUT38
NC
NC
NC
VSSP
VSSP
VSSP
VSSP
VSSSUB
VSSP
NC
VPP
VPP
VPP
VPP
50
STV7617, STV7617D, STV7617U
PIN CONNECTIONS (NO SLUG)
(TQFP100)
OUT65 77
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
76 75 74 73 72 71 70 69 68 67 66
OUT64
SOUT
OUT2
OUT1
VSSLOG
VSSLOG
STB
CLK
SEL
BLK
VSSP
VSSP
VSSP
VSSP
SIN
HIZ
F/R
VCC
NC
NC
VPP
VPP
VPP
VPP
OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT33 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39
STV7617
TQFP100 (Top View)
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
OUT36
OUT37
OUT38
OUT28
OUT29
OUT30
OUT31
OUT32
OUT33
OUT34
OUT35
NC
NC
NC
VPP
VSSSUB
VSSP
VSSP
VSSP
VSSP
VSSP
NC
VPP
VPP
VPP
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STV7617, STV7617D, STV7617U
PIN ASSIGNMENT
(TQFP100)
Pin Number TQFP100 Slug-dow n/ TQFP100 Slug-up TQFP100 No slug 88 88 34-35-41-42 34-35-41-42 78-79-97-98 30-31-44-45 46-81-82-94-95 83-93 32 77 to 48, 40 to 36, 28 to 1, 100-99 91 90 89 87 86 85 84 92 29-33-43-47-80-96 78-79-97-98 30-31-32-45 46-81-82-94-95 83-93 44 99-100, 1 to 28, 36 to 40, 48 to 77 85 86 87 89 90 91 92 84 29-33-43-47-80-96 Symbol VCC VPP VSSP VSSLOG VSSSUB OUT1 to OUT 65 SOUT (SIN) CLK ST B BLK HIZ SIN (SOUT) SEL F/ R NC Type Supply Supply Ground Ground Ground Output Output Input Input Input Input Input Input Input Function 5 V Logic Supply High Voltage Supply of power outputs Ground of power outputs Logic Ground Substrate Ground Power Output Shift Register Data Output Clock of data shift register Latch of data to outputs Power Output Blanking Control Power Output High Impedance Control Shift Register Data Input Selection of number of power outputs Selection of shift direction Not connected
PIN ASSIGNMENT (Power Outputs)
Output Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Number Slug-dow n/ No slug 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 Slug-u p 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 17 18 19 20 Output Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Number Slug-do wn/ No slug 55 54 53 52 51 50 49 48 40 39 38 37 36 28 27 26 25 24 23 22 21 20 Slug-up 21 22 23 24 25 26 27 28 36 37 38 39 40 48 49 50 51 52 53 54 55 56 Output Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Pin Number Slug-down/ No slug 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 Slug-up 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77
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STV7617, STV7617D, STV7617U
BLOCK DIAGRAM
F/R SWITCH SEL CLK SIN (SOUT)
P1 S1
65-BIT SHIFT REGISTER
P65 S65
SOUT (SIN)
STB
Q1 Q2
LATCH
Q64Q65
VCC BLK VCC HIZ
VCC VSSS UB VSSP VSSL OG VPP
STV7617
VSSP
VPP
VSSP
VPP
OUT1
OUT64
OUT65
CIRCUIT DESCRIPTION
The STV7617 contains all the logic and the power circuits necessary to drive rows of a Plasma Display Panel (PDP). Data is shifted at each low to high transition of the (CLK) shift clock. After 64 or 65 shifts (depending on SEL) the first bit presented at (SIN) is available at the serial output (SOUT). This output can be used to cascade several drivers to perform any vertical resolution. CLK, STB, SIN and SOUT inputs are Smith trigger inputs. BLK and HIZ logical inputs are internally pulled to level "1". The maximum frequency of the shift clock is 8 MHz. Shift register outputs (P1, ... P65) are transferred from the shift register into the latch stage when the latch input (STB) is at low level. Table 1 : Output State Configuration
STB * L H * * BLK L L L H H HIZ L H H L H Output State High impedance Inverted copy of input data Data latched Low level High Level
Sustain current must not be sunk in the power outputs to VPP when the power supply is applied and output state is in HIZ or at high state. VSSSUB and VSSLOG must be connected as close as possible to the logical reference ground of the application. Table 2 : Shift Register Truth Table
F/R H H L L CLK Rise L or H Rise L or H SIN In In Out Out SOUT Out Out In In Comments Forward Shift Steady Reverse Shift Steady
Table 3 : Power Output Configuration
SEL L L H H F/R L H L H Number of Outpu ts 64 64 65 65 Comments Out 1 is in Hi-Z mode (outputs 65 to 2 powered) Out 65 is in Hi-Z mode (outputs 1 to 64 powered) Out 65 to Out 1 powered Out 1 to Out 65 powered
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STV7617, STV7617D, STV7617U
ABSOLUTE MAXIMUM RATINGS
Symbol VCC OUTi VIN V OUT VPOUT IPOUT IDOUT Tjmax Toper Tstg Parameter Logic Supply (Pin 88)* Output Pins (1 to 28, 36 to 40, 48 to 77, 99, 100) Logic Input Voltage (Pins 84, 86, 87, 89, 90, 91, 92)* Logic Output Voltage (Pin 85)* Driver Output Voltage (scanning mode) Driver Output Current (1) (4) Diode Output Current (3) (4) Junction Temperature Operating Temperature Storage Temperature Value -0.3, +7 -0.3, +100 -0.3, VCC +0.3 -0.3, VCC + 0.3 -0.3, +100 -100, +1 A 700 +150 -20, +85 -20, +150 Unit V V V V V mA mA C C C
* In case of STV7617D
THERMAL DATA
Symbol Rth(j-a) Tjoper Rth(j-a) Parameter Junction-ambient Thermal Resistance (1) Maximum Operating Junction (1) Junction-ambient Thermal Resistance (5) Value 20 125 40 Unit C/W C C/W
Note 1 For TQFP100 packaging and slug soldered on printed circuit board. Note 2 Through one power output. Note 3 Through all power outputs (see test diagram): with Power dissipation lower or equal than Ptot and Junction temperature lower or equal than Tjmax and VPP = VSSP. Note 4 These parameters are measured during ST's internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts. Note 5 TQFP soldered on 4 layers Printed Circuit Board.
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STV7617, STV7617D, STV7617U
ELECTRICAL CHARACTERISTICS
(VCC = 5 V, VPP = 90 V, VSSP = 0 V, VSSLOG = 0 V, V SSSUB = 0 V, Tamb = 25C, fCLK = 8 MHz, unless otherwise specified)
Symbol SUPPLY VCC ICCH ICCL VPP IPPH Parameter Logic Supply Voltage Logic Supply Current Logic Supply Current Power Output Supply Voltage Power Output Supply Current (steady outputs) fCLK = 8 MHz Test Condi tions Min. 4.5 20 Typ. 5 5 Max. 5.5 100 90 100 Unit V A mA V A
OUTPUT OUT1-OUT65 VPOUTH Power Output High Level VPOUTH VPOUTL VPOUTL-P VDOUTH VDOUTL SOUT VOH VOL Power Output High Level Power Output Low Level Power Output Low Level-pulsed mode Output Diode High Level Output Diode Low Level Logic Output High Level Logic Output Low Level
IPOUTH = - 20 mA I POUTH = - 15mA, V PP = 40 V IPOUTL = + 400 mA IPOUTL-P = 850 mA (6) IDOUTH = +400 mA (7) (8) IDOUTL = - 400 mA (7)(8) I OH = -1 mA IOL = +1 mA
83 30 4 0.8 VCC -
86 33 2.5 1.7 -1.2 4.2 0.1 -
5 15 5 -5 0.4 0.2VCC 10 -10 -40
V V V V V V V V V V A A A
INPUT (CLK, STB, BLK, HIZ, SIN, SEL) VIH Input High Level VIL IIH IIL Input Low Level High Level Input Current Low Level Input Current CLK, SIN, STB, SEL, BLK, HIZ VIH = VCC VIL = 0 V
-
Note 6 Peak current - Pulse mode 720 Hz - 0.2%. Duty cycle - VCC = 5.5 V 0.2 V. Note 7 Compatible with power dissipation and Tjoper 125C. Note 8 See test diagram page 12.
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STV7617, STV7617D, STV7617U
AC TIMING REQUIREMENTS
(VCC = 4.5 V to 5.5 V, Tamb = -20 to +85C, input signals max leading edge & trailing edge (tR, tF) = 10 ns)
Symbol tWHCLK tWLCLK tSDAT tHDAT tDSTB tSSTB tSTB tBLK tHIZ Parameter Duration of clock (CLK) pulse at high level Duration of clock (CLK) pulse at low level Set-up Time of data input before clock (low to high) transition Hold Time of data input after clock (low to high) transition Minimum Delay to latch STB after clock (low to high) transition Set-up Time STB before clock (low to high) transition Latch STB Low Level Pulse Duration Blanking (BLK) Pulse Duration High Impedance HIZ Pulse Duration Min. 40 40 10 20 25 10 20 500 500 Typ. Max. Unit ns ns ns ns ns ns ns ns ns
AC TIMING CHARACTERISTICS
(VCC = 5 V, VPP = 90 V, VSSP = 0 V, VSSLOG = 0 V, VSSSUB = 0 V, Tamb = 25C, VILMax. = 0.2 Vcc, VIHMin. = 0.8 VCC, VOH = 4.0 V, VOL = 0.4 V, unless otherwise specified)
Symbol tCLK tRDAT tFDAT tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tPHZ5 tPLZ5 tPZH5 tPZL5 tROUT tFOUT Data Clock Period Logical Data Output Rise Time Logical Data Output Fall Time Delay of logic data output (high to low transition) after clock (CLK) transition (CL=10pF) Delay of logic data output (low to high transition) after clock (CLK) transition (CL=10 pF) Delay of power output change (high to low transition) after clock (CLK) transition Delay of power output change (low to high transition) after clock (CLK) transition Delay of power output change (high to low transition) after Latch (STB) transition Delay of power output change (low to high transition) after Latch (STB) transition Delay of power output change (high to low transition) to blank (BLK) transition Delay of power output change (low to high transition) to blank (BLK) transition Delay of power output change (high to Hi-Z transition) after high impedance (HIZ)(9) Delay of power output change (low to Hi-Z transition) after high impedance (HIZ)(9) Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (9) Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (9) Power Output Rise Time (10) Power Output Fall Time (10) Parameter Min. Typ. Max. Unit 125 12 10 37 42 110 115 80 95 75 75 40 80 75 40 175 35 20 20 50 60 180 180 165 165 160 160 160 160 160 160 350 150 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 9 See test diagram page 12. Note 10 One output among 64, loading capacitor COUT = 200pF, other outputs at low level.
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STV7617, STV7617D, STV7617U
Figure 1: AC Characteristics Waveform
tCLK tWHCLK tWLCLK "1" CLK 50% 50% tSDAT 50% "0" tHDAT "1" SIN 50% 50% "0" tFDAT SOUT 90% 10% tRDAT tPLH1 tSSTB tDSTB tSTB "1" STB tPHL2 90% 10% tPLH2 tBLK/POL "1" HIZ (BLK = H) 50% tPLH4 50% "0" tPHL4 90% OUTn 10% "0" tHIZ "1" HIZ (BLK = L) tROUT 90% 10% 90% 10% tFOUT 50% tPHZ5 90% 10% tPLZ5 50% "0" tPZH5 60% 40% tPZL5 "1" "1" tPLH3 50% 50% "0" tPHL3 "1" OUTn 90% 10% "0" tPHL1 "1" 90% 10% "0"
OUTn
"0"
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STV7617, STV7617D, STV7617U
Figure 2: Test Configuration
VPP=VSSP VPP=VSSP
VDOUTH
IDOUTH
VDOUTL V SSP VSSP
IDOUTL
Output sinking current as positive value, sourcing current as negative value
VPP OUT
R
VPP/2
VDOUT
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STV7617, STV7617D, STV7617U
INPUT/OUTPUT CHARACTERISTICS
Figure 3: BLK, HIZ Input
VCC
Figure 5: SIN, SOUT Input
VCC VCC
VCC
SIN, SOUT VCC
BLK, HIZ
GNDLOG
GNDLOG GNDSUB
GNDSUB
Figure 4: F/R, SEL, CLK, STB Input
VCC VCC
Figure 6: Power Output
VPP
F/R, SEL CLK, STB
OUT1 to OUT 65
GNDLOG
GNDSUB
VSSP
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STV7617, STV7617D, STV7617U
PACKAGE MECHANICAL DATA (SLUG-DOWN)
100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)
S1 100 e A1 76 0,075 mm 0.03 inch 75
SEATING PLANE
A A2
1
25
51
c
26
D3 D1 D
50
L1
L
E3 E1 E
S
0,25 mm .010 inch
GAGE PLANE
K
Dimensions
Min.
Millimeters Typ.
A A1 0.05 0.002 A2 1.35 1.40 0.053 B 0.17 0.22 0.007 C 0.09 0.004 D 16.00 D1 14.00 D3 12.00 e 0.50 E 16.00 E1 14.00 E3 12.00 L 0.45 0.60 0.75 0.018 L1 1.00 K 0 (Min.), 7 (Max.) Slug Dimension For L/Frame Pad Size 10.00 x 10.00 mm H 9.85 S 8.80 0.346 S1 8.80 0.346
Max. 1.60 0.15 1.45 0.27 0.20
Min.
Inches Typ.
B
H
0.055 0.009 0.630 0.551 0.472 0.20 0.630 0.551 0.472 0.024 0.039
Max. 0.063 0.006 0.057 0.011 0.008
0.030
0.388
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STV7617, STV7617D, STV7617U
PACKAGE MECHANICAL DATA (SLUG-UP)
100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)
S1 100 e A1 76 0,075 mm 0.03 inch 75
SEATING PLANE
A A2
1
25
51
E3 E1 E
S
26
D3 D1 D
50
L1
L
0,25 mm .010 inch
GAGE PLANE
K
Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K H S S1
Millimeters Min. 0.05 1.35 0.17 0.09 16.00 14.00 12.00 0.50 16.00 14.00 12.00 0.45 0.60 1.00 0 (Min.), 7 (Max.) 9.85 8.80 8.80 0.346 0.346 0.75 0.018 1.40 0.22 Typ. Max. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 Min.
B
Slug Dimension For L/Frame Pad Size 10.00 x 10.00 mm 0.388
H
c
Inches Typ. Max. 0.063 0.006 0.055 0.009 0.630 0.551 0.472 0.20 0.630 0.551 0.472 0.024 0.039 0.030 0.057 0.011 0.008
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STV7617, STV7617D, STV7617U
PACKAGE MECHANICAL DATA (NO SLUG)
100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)
A A2 100 e A1 76 0,075 mm 0.03 inch 75
SEATING PLANE
1
25
51
c
26
D3 D1 D
50
L1
L
E3 E1 E
0,25 mm .010 inch
GAGE PLANE
K
Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K
Millimeters Min. 0.05 1.35 0.17 0.09 16.00 14.00 12.00 0.50 16.00 14.00 12.00 0.45 0.60 1.00 0 (Min.), 7 (Max.) 0.75 0.018 1.40 0.22 Typ. Max. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 Min.
B
Inches Typ. Max. 0.063 0.006 0.055 0.009 0.630 0.551 0.472 0.20 0.630 0.551 0.472 0.024 0.039 0.030 0.057 0.011 0.008
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STV7617, STV7617D, STV7617U
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www .st.com
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